Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling

A semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1–3.6 nm). As a multiplier to a simple analytical model [1], [2], a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N, P, Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence band (HVB) in dual-gate poly-Si1 Ge -gated ( = 0 or 0 25) CMOS devices for various gate oxide thicknesses. In addition, this model can also be employed to determine the physical oxide thickness from – data with high sensitivity. It is particularly sensitive in the very-thin-oxide regime, where – extraction happens to be difficult or impossible (because of the presence of the large tunneling current).